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r ev . 2.5 i w1710 p age 1 n ovembe r 27, 2012 1.0 features primary-side feedback eliminates opto-isolators and simplifes design quasi-resonant operation for highest overall effciency ez-emi ? design to easily meet global emi standards up to 130 khz switching frequency enables small adapter size very tight output voltage regulation no external compensation components required complies with cec/epa no-load power consumption and average effciency regulations built-in output constant-current control with primary-side feedback low start-up current (10 a typical) built-in soft start built-in short circuit protection and output overvoltage protection optional ac line under/overvoltage protection pfm operation at light load current sense resistor short protection overtemperature protection figure 3.1 : typical application circuit 2.0 description the IW1710 is a high performance ac/dc power supply controller which uses digital control technology to build peak current mode pwm fyback power supplies. the device operates in quasi-resonant mode at heavy load to provide high effciency along with a number of key built-in protection features while minimizing the external component count, simplifying emi design and lowering the total bill of material cost. the IW1710 removes the need for secondary feedback circuitry while achieving excellent line and load regulation. it also eliminates the need for loop compensation components while maintaining stability over all operating conditions. pulse-by-pulse waveform analysis allows for a loop response that is much faster than traditional solutions, resulting in improved dynamic load response. the built-in current limit function enables optimized transformer design in universal off-line applications over a wide input voltage range. the ultra-low operating current at light load ensures that the IW1710 is ideal for applications targeting the newest regulatory standards for average effciency and standby power. 3.0 applications cable/dsl modems, wlan access points and voip gateways. l n v out rtn + + + u1 IW1710 optional ntc thermistor nc v sense v in sd v cc output i sense gnd 1 2 3 8 7 6 4 5 IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 2 n ovembe r 27, 2012 parameter symbol value units dc supply voltage range (pin 8, i cc = 20ma max) v cc -0.3 to 18 v dc supply current at v cc pin i cc 20 ma output (pin 7) -0.3 to 18 v v sense input (pin 2, i vsense 10 ma) -0.7 to 4.0 v v in input (pin 3) -0.3 to 18 v i sense input (pin 6) -0.3 to 4.0 v sd input (pin 4) -0.3 to 18 v power dissipation at t a 25c p d 526 mw maximum junction temperature t j max 125 c storage temperature t stg C65 to 150 c thermal resistance junction-to-ambient ja 160 c/w esd rating per jedec jesd22-a114 2,000 v latch-up test per jedec 78 100 ma absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. for maximum safe operating conditions, refer to electrical characteristics in section 6.0. 4.0 pinout description pin # name type pin description 1 nc - no connection. 2 v sense analog input auxiliary voltage sense (used for primary side regulation). 3 v in analog input rectifed ac line average voltage sense. 4 sd analog input external shutdown control. connect to ground through a resistor if not used. (see section 10.16) 5 gnd ground ground. 6 i sense analog input primary current sense (used for cycle-by-cycle peak current control and limit). 7 output output gate drive for external mosfet switch. 8 v cc power input power supply for control logic and voltage sense for power-on reset circuitry . IW1710 nc v sense v in sd v cc output i sense gnd 1 2 3 8 7 6 4 5 5.0 absolute maximum ratings IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 3 n ovembe r 27, 2012 v cc = 12 v, -40c t a 85c, unless otherwise specifed (note 1) parameter symbol test conditions min typ max unit v in section (pin 3) start-up low voltage threshold v instlow t a = 25c, positive edge 335 369 406 mv start-up current i inst v in = 10 v, c vcc = 10 f 10 15 a shutdown low voltage threshold v uvdc t a = 25c, negative edge 201 221 243 mv input impedance z in after start-up 25 k w v sense section (pin 2) input leakage current i bvs v sense = 2 v 1 a nominal voltage threshold v sense(nom) t a =25c, negative edge 1.523 1.538 1.553 v output ovp threshold - 01 (note 2) v sense(max) t a =25c, negative edge 1.754 1.846 1.938 v output ovp threshold - 11 (note 2) v sense(max) t a =25c, negative edge, load = 100% 1.797 1.892 1.987 v output ovp threshold - 21 (note 2) v sense(max) t a =25c, negative edge, load = 100 % 1.836 1.933 2.030 v output section (pin 7) output low level on-resistance r ds(on)lo i sink = 5 ma 40 w output high level on-resistance r ds(on)-hp i source = 5 ma 75 w rise time (note 2) t r t a = 25c, c l = 330 pf 10% to 90% 200 300 ns fall time (note 2) t f t a = 25c, c l = 330 pf 90% to 10% 40 60 ns maximum switching frequency -01, -11, -21 (note 3) f sw(max) any combination of line and load 130 140 khz v cc section (pin 8) maximum operating voltage (note 2) v cc(max) 16 v start-up threshold v cc(st) v cc rising 10.8 12 13.2 v undervoltage lockout threshold v cc(uvl) v cc falling 5.5 6.0 6.6 v operating current i ccq c l = 330 pf, v sense = 1.5 v 3.5 5 ma 6.0 electrical characteristics IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 4 n ovembe r 27, 2012 parameter symbol test conditions min typ max unit i sense section (pin 6) peak limit threshold v peak 1.045 1.1 1.155 v isense short protection reference v rsns 0.127 0.15 0.173 v cc regulation threshold limit (note 2) v reg-th 1.0 v sd section (pin 4) shutdown threshold v sd-th t a = 25c 0.95 1.0 1.05 v shutdown threshold in startup (note 2) v sd-th(st) 1.2 v input leakage current i bvsd v sd = 1.0 v 1 a pull down resistance r sd t a = 25c 7916 8333 8750 w pull up current source i sd t a = 25c 96 107 118 a 6.0 electrical characteristics (cont.) notes: note 1. adjust v cc above the start-up threshold before setting at 12 v. note 2. these parameters are not 100% tested, guaranteed by design and characterization. note 3. operating frequency varies based on the line and load conditions, see theory of operation for more details. v cc = 12 v, -40c t a 85c, unless otherwise specifed (note 1) IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 5 n ovembe r 27, 2012 7.0 typical performance characteristics 0.0 0.0 6.0 3.0 9.0 2.0 6.0 10.0 14.0 v cc (v) v cc supply start-up current (a) 4.0 8.0 12.0 figure 7.1 : v cc vs. v cc supply start-up current -50 12.0 -25 25 75 125 ambient temperature (c) v cc start-up threshold (v) 0 50 100 12.2 11.8 11.6 figure 7.2 : start-up threshold vs. temperature -50 -25 25 75 125 ambient temperature (c) % deviation of switching frequency from ideal 0 50 100 0.3 % -0.3 % -0.9 % -1.5 % figure 7.3 : % deviation of switching frequency to ideal switching frequency vs. temperature 1.518 -50 1.538 1.528 1.548 -25 25 75 125 ambient temperature (c) internal reference voltage (v) 0 50 100 figure 7.4 : internal reference vs. temperature IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 6 n ovembe r 27, 2012 8.0 functional block diagram 9.0 theory of operation figure 8.1 : IW1710 functional block diagram ? + v in gnd enable v cc 5 sd 4 v sense v fb v vms v ipk output i sense 6 1.1 v v sd-th 0 v ~ 1 v v in_a 0.2 v ~ 2.0 v i peak adc v ocp ? start-up dac ? + + ? 2 3 8 digital logic control signal conditioning gate driver 7 enable z vin 25 k i sd 60 k r sd detection switch the IW1710 is a digital controller which uses a proprietary primary-side control technology to eliminate the opto- isolated feedback and secondary regulation circuits required in traditional designs. this results in a low-cost solution for ac/dc adapters. the IW1710 uses critical discontinuous conduction mode (cdcm) or pulse width modulation (pwm) mode at high output power levels and switches to pulse frequency modulation (pfm) mode at light load to minimize power dissipation to meet epa 2.0 specifcation. furthermore, iwatts digital control technology enables fast dynamic response, tight output regulation, and full featured circuit protection with primary-side control. referring to the block diagram in figure 8.1, the digital logic control block generates the switching on-time and off-time information based on the line voltage and the output voltage feedback signal and provides commands to dynamically control the external mosfet current. the system loop is compensated internally by a digital error amplifer. adequate system phase and gain margin are guaranteed by design and no external analog components are required for loop compensation. the IW1710 uses an advanced digital control algorithm to reduce system design time and improve reliability. furthermore, accurate secondary constant-current operation is achieved without the need for any secondary-side sense and control circuits. the built-in protection features include overvoltage protection (ovp), output short circuit protection (scp) and soft-start, ac line brown out, overcurrent protection, and isense fault protection. also the IW1710 automatically shuts down if it detects any of its sense pins to be either open or short. iwatts digital control scheme is specifcally designed to address the challenges and trade-offs of power conversion design. this innovative technology is ideal for balancing new regulatory requirements for green mode operation with more practical design considerations such as lowest possible cost, smallest size and highest performance output control. IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 7 n ovembe r 27, 2012 9.1 pin detail pin 2 C v sense sense signal input from auxiliary winding. this provides the secondary voltage feedback used for output regulation. pin 3 C v in sense signal input from the rectifed line voltage. v in is used for line regulation. the input line voltage is scaled down using a resistor network. it is used for input undervoltage and overvoltage protection. this pin also provides the supply current to the ic during start-up. pin 4 C sd external shutdown control. if the shutdown control is not used, this pin should be connected to gnd via a resistor. (see section 10.16). pin 5 C gnd ground. pin 6 C i sense primary current sense. used for cycle by cycle peak current control. pin 7 C output gate drive for the external mosfet switch. pin 8 C v cc power supply for the controller during normal operation. the controller will start up when v cc reaches 12 v (typical) and will shut-down when the v cc voltage is below 6 v (typical). a decoupling capacitor should be connected between the v cc pin and gnd. 9.2 start-up prior to start-up the v in pin charges up the v cc capacitor through the diode between v in and v cc (see figure 8.1). when v cc is fully charged to a voltage higher than the start- up threshold v cc(st) , the enable signal becomes active and enables the control logic; the v in switch turns on, and the analog-to-digital converter begins to sense the input voltage. once the voltage on the v in pin is above v instlow , the IW1710 commences soft start function. an adaptive soft-start control algorithm is applied at startup state, during which the initial output pulses will be small and gradually get larger until the full pulse width is achieved. the peak current is limited cycle by cycle by ipeak comparator. if at any time the v cc voltage drops below v cc(uvl) threshold then all the digital logic is reset. at this time v in switch turns off so that the v cc capacitor can be charged up again towards the start-up threshold. v cc v cc(st) enable start-up sequencing v in figure 9.1 : start-up sequencing diagram 9.3 understanding primary feedback figure 9.2 illustrates a simplifed fyback converter. when the switch q1 conducts during t on (t) , the current i g (t) is directly drawn from rectifed sinusoid v g (t) . the energy e g (t) is stored in the magnetizing inductance l m . the rectifying diode d1 is reverse biased and the load current i o is supplied by the secondary capacitor c o . when q1 turns off, d1 conducts and the stored energy e g (t) is delivered to the output. + v in (t) t s (t) i o v o v aux n:1 d1 q1 v aux c o v g (t) i g (t) + ? i in (t) i d (t) figure 9.2 : simplifed flyback converter in order to tightly regulate the output voltage, the information about the output voltage and load current needs to be accurately sensed. in the dcm fyback converter, this information can be read via the auxiliary winding. during the q 1 on-time, the load current is supplied from the output flter capacitor c o . the voltage across l m is v g (t) , assuming the voltage dropped across q 1 is zero. the current in q 1 ramps up linearly at a rate of: () () gg m di t v t dt l (9.1) IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 8 n ovembe r 27, 2012 at the end of on-time, the current has ramped up to: _ () () g on g peak on m vt t it l = (9.2) this current represents a stored energy of: 2 _ () 2 m g g peak on l e it = (9.3) when q 1 turns off, i g (t) in l m forces a reversal of polarities on all windings. ignoring the communication-time caused by the leakage inductance l k at the instant of turn-off, the primary current transfers to the secondary at a peak amplitude of: _ () ( ) p d g peak on s n it i t n = (9.4) assuming the secondary winding is master and the auxiliary winding is slave. v aux 0v v aux = -v in x n aux n p v aux = v o x n aux n s figure 9.3 : auxiliary voltage waveforms the auxiliary voltage is given by: () aux aux o s n v vv n = +? (9.5) and refects the output voltage as shown in figure 9.3. the voltage at the load differs from the secondary voltage by a diode drop and ir losses. the diode drop is a function of current, as are ir losses. thus, if the secondary voltage is always read at a constant secondary current, the difference between the output voltage and the secondary voltage will be a fxed v . furthermore, if the voltage can be read when the secondary current is small; for example, at the knee of the auxiliary waveform (see figure 9.3), then v will also be small. with the IW1710, v can be ignored. the real-time waveform analyzer in the IW1710 reads the auxiliary waveform information cycle by cycle. the part then generates a feedback voltage v fb . the v fb signal precisely represents the output voltage and is used to regulate the output voltage. 9.4 constant voltage operation after soft-start has been completed, the digital control block measures the output conditions. it determines output power levels and adjusts the control system according to a light load or a heavy load. if this is in the normal range, the device operates in the constant voltage (cv) mode, and changes the pulse width (t on ), and off time (t off ) in order to meet the output voltage regulation requirements. during this mode the pwm switching frequency is between 30 khz and 130 khz, depending on the line and load conditions. if less than 0.2 v is detected on v sense it is assumed that the auxiliary winding of the transformer is either open or shorted and the IW1710 shuts down. 9.5 dynamic load transient there are three components that compose the voltage drop during a load transient event. v drop(cable) is the drop in voltage due to the increased current going through the connector and/or the cable. () drop cable cable out v ri = ? (9.6) the second component which affects the voltage drop during load transient is v drop(sense) . this voltage drop is the drop in voltage before the v sense signal is able to show a signifcant drop in output voltage. this is determined by v min or the reference voltage at which a load transient is detected. the smaller the v min is the smaller this drop in voltage is. ( ) () ( ) ( ) (min) () out pcb drop sense sense nom sense sense nom v v vv v = ? (9.7) keep in mind that a smaller v min is less tolerant of noise and distortions in v sense than a larger one. the fnal drop in voltage is due to the time from when v sense drops v min to when the next v sense signal appears. in the worst case condition this is how much voltage drops during the longest switching period. (no load) () out p drop ic out it v c = (9.8) a larger output capacitance in this case greatly reduces the v drop(ic) . IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 9 n ovembe r 27, 2012 when the IW1710 detects the output voltage to be signifcantly higher than the nominal output voltage, the device begins to increase the switching period which lowers the output voltage. t period(clamp) refers to the maximum switching period to which the IW1710 increases to when an output voltage is detected to be signifcantly over the nominal. during fast load changes the output voltage may not have time to settle before the load is changed. thus for this case when the power supply goes from light load to heavy load prior to output voltage settling t period(clamp) substitutes t period(pfm) in equation 9.8. 9.6 valley mode switching in order to reduce switching losses in the mosfet and emi, the IW1710 employs valley mode switching when i out is above 50%. in valley mode switching, the mosfet switch is turned on at the point where the resonant voltage across the drain and source of the mosfet is at its lowest point (see figure 9.4). by switching at the lowest v ds , the switching loss will be minimized. g a t e v d s figure 9.4 : valley mode switching turning on at the lowest v ds generates lowest dv/dt, thus valley mode switching can also reduce emi. to limit the switching frequency range, the IW1710 can skips valleys (seen in the frst cycle in figure 9.4) when the switching frequency becomes too high. IW1710 provides valley mode switching during constant output current operation. so, the emi and switching losses are still minimized during cc mode. this feature is superior to other quasi-resonant technologies which only support valley mode switching during constant voltage operation. this is benefcial to applications, such as chargers, where the power supply mainly operates in cc mode. 9.7 constant current operation the constant current mode (cc mode) is useful in battery charging applications. during this mode of operation the IW1710 will regulate the output current at a constant level regardless of the output voltage, while avoiding continuous conduction mode. to achieve this regulation the IW1710 senses the load current indirectly through the primary current. the primary current is detected by the i sense pin through a resistor from the mosfet source to ground. output voltage output current i out(cc) v nom cv mode cc mode figure 9.5 : power envelope 9.8 pfm mode at light load the IW1710 normally operates in a fxed frequency pwm or critical discontinuous conduction mode when i out is greater than approximately 10% of the specifed maximum load current. as the output load i out is reduced, the on-time t on is decreased. at the moment that the load current drops below 10% of nominal, the controller transitions to pulse frequency modulation (pfm) mode. thereafter, the on- time will be modulated by the line voltage and the off-time is modulated by the load current. the device automatically returns to pwm mode when the load current increases. 9.9 variable frequency operation at each of the switching cycles, the falling edge of v sense will be checked. if the falling edge of v sense is not detected, the off-time will be extended until the falling edge of v sense is detected. the maximum allowed transformer reset time is 120 s. when the transformer reset time reaches this maximum reset time, the IW1710 immediately shuts off. 9.10 internal loop compensation the IW1710 incorporates an internal digital error amplifer with no requirement for external loop compensation. for a typical power supply design, the loop stability is guaranteed to provide at least 45 degrees of phase margin and C20db of gain margin. IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 10 n ovembe r 27, 2012 9.11 voltage protection functions the IW1710 includes functions that protect against input line undervoltage (uv) and the output overvoltage (ovp). the input voltage is monitored by the v in pin and the output voltage is monitored by the v sense pin. if the voltage at these pins exceed their respective undervoltage or overvoltage thresholds the IW1710 shuts down immediately. however, the ic remains biased which discharges the v cc supply. once v cc drops below the uvlo threshold, the controller resets itself and then initiates a new soft-start cycle. the controller continues attempting start-up until the fault condition is removed. 9.12 pcl, oc and srs protection peak-current limit (pcl), over-current protection (ocp) and sense-resistor short protection (srsp) are features built-into the IW1710. with the i sense pin the IW1710 is able to monitor the primary peak current. this allows for cycle by cycle peak current control and limit. when the primary peak current multiplied by the i sense sense resistor is greater than 1.1 v over current is detected and the ic will immediately turn off the gate drive until the next cycle. the output driver will send out switching pulse in the next cycle, and the switching pulse will continue if the ocp threshold is not reached; or, the switching pulse will turn off again if the ocp threshold is still reached. if the i sense sense resistor is shorted there is a potential danger of the over current condition not being detected. thus the ic is designed to detect this sense-resistor-short fault after the start up, and shutdown immediately. the v cc will be discharged since the ic remains biased. once v cc drops below the uvlo threshold, the controller resets itself and then initiates a new soft-start cycle. the controller continues attempting start-up, but does not fully start-up until the fault condition is removed. 9.13 shutdown the shutdown (sd) pin in the IW1710 provides protection against overtemperature (otp) and additional overvoltage (ovp) for the power supply. the IW1710 switches between monitoring overtemperature fault and overvoltage fault. in order to detect the resistance in the ntc for an overtemperature fault, the IW1710 connects a current source to the sd pin and checks the voltage on the pin. to ensure that the current source is settled before the voltage is checked both otp and ovp are detected on the last cycle, as depicted in fgure 9.6. vgate detection switch ovp detection otp detection detection switch: when switch is low sd pin is connected to r when switch is high sd pin is connected to a current source i sd sd figure 9.6 : sd pin detection cycles during an overvoltage monitor cycle the sd pin is connected to a resistance internal to the chip, r sd , to ground and the voltage on the sd pin is observed. v sd -t h s d p i n o v p / o t p f a u l t d e t e ct IW1710 i sd figure 9.7 : internal function of sd pin IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 11 n ovembe r 27, 2012 10.0 design example 10.1 design procedure this design example gives the procedure for a fyback converter using IW1710. refer to figure 12.1 for the application circuit. the design objectives for this adapter are given in table 10.1. it meets ul, iec, and cec requirements. figure 10.1 : IW1710 design flow chart parameter symbol range input voltage v in 85 - 264 v rms frequency f in 47 - 64 hz no load input p in 100 mw output voltage v out(cable) 12.0 v output current i out 1.2 a output ripple v ripple < 100 mv power out p out 15 w epa 2.0 effciency h 80% table 10.1 : IW1710 design specifcation table 10.2 determine part number based on design specifcations, choose the most suitable part for the design. for more information on the options see section 14.0. use equation 10.1 for v out in the following calculations, where v fd is the forward voltage of the output diode. () out out cable cabledrop fd vv v v = ++ (10.1) for this example there is no cable so v cabledrop is 0 v , assuming v fd is 0.5, v out is: 12.0 0 0.5 12.5 out v vv v v = ++ = 10.3 input selection v in resistors are chosen primarily to scale down the input voltage for the ic. the default scale factor for the input voltage in the ic is 0.0043 and the internal impedance of this pin is z in (25 k w ). therefore, the v in resistors should equate to: 0.0043 in vin in z rz = ? (10.2) from equation 10.2, ideally r vin should be 5.79 m w. a lower value of r vin can decrease the startup time of the power supply. the value of r vin affects the (v in t on ) limits of the ic. ( ) ( ) limit 720 s 0.0043 in on in vin in v vt z rz ?m ?= + (10.3) ( ) ( ) 135 0.0043 in on pfm in vin in vs vt z rz ?m ?= + (10.4) d e t e r m i n e t h e d e s i g n s p e c i f i c a t i o n s ( v o u t , i o u t _ m a x , v i n _ m a x , v i n _ m i n , ? l i n e , r i p p l e s p e c i f i c a t i o n ) d e t e r m i n e t u r n s r a t i o d e t e r m i n e i n p u t b u l k c a p a c i t a n c e d e t e r m i n e c u r r e n t s e n s i n g r e s i s t o r d e t e r m i n e m a g n e t i z i n g i n d u c t a n c e d e t e r m i n e p r i m a r y t u r n s d e t e r m i n e s e c o n d a r y t u r n s c a n y o u w i n d t h i s t r a n s f o r m e r ? d e t e r m i n e b i a s t u r n s a n d v c c c a p a c i t a n c e d e t e r m i n e v s e n s e r e s i s t o r s d e t e r m i n e o u t p u t c a p a c i t a n c e d e t e r m i n e s n u b b e r n e t w o r k d e t e r m i n e current sensing filter f i n i s h n o d e t e r m i n e r v i n r e s i s t o r s d e t e r m i n e o p e r a t i n g v i n t o n l i m i t y e s d e t e r m i n e part number IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 12 n ovembe r 27, 2012 for this example r vin is chosen to be 5.1 m therefore, ( ) ( ) limit 720 s 0.0043 635 25 5.1 25 in on v v t vs k mk ?m ? = = ?m w w+ w ( ) ( ) 135 0.0043 119 25 5.1 25 in on pfm vs v t vs k mk ?m ? = = ?m w w+ w keep in mind, by changing r vin to be something other than 5.79 m w the minimum and maximum input voltage for start- up also changes. since the IW1710 uses the exact scaled value of v in for its calculations, there should be a flter capacitor on the input pin to flter out any noise that may appear on the v in signal. this is especially important for line in surge conditions. 10.4 turns ratio the maximum allowable turns ratio between the primary and secondary winding is determined by the minimum detectable reset time of the transformer during pfm mode. ( ) (max) (min) in on pfm tr reset out vt n tv ? = (10.5) setting t reset(min) at 1.5 s, (max) 119 6.3 1.5 12.5 tr vs n sv ?m = = m for this example a turns ratio of 6 is chosen. keep in mind in valley mode switching the higher the turns ratio the lower the v ds turn-on voltage, which means less switch turn-on power loss. also consider the voltage stress on the mosfet (v ds ) is higher with an increase in turns ratio. the voltage stress on the output diode is lower with an increase in turns ratio respectively. 10.5 operating maximum (v in t on ) maximum operating v in t on or (v in t on ) max for valley mode switching is traditionally designed at full load and lowest input voltage. for the IW1710, two constraints (equation 10.6 and 10.7) need to be satisfed so that indeed (v in t on ) max occurs at full load and lowest input voltage. ( min) 1 100 p qr t khz > (10.6) ' ( min) 1 110 p qr res tt khz >+ (10.7) t res is the v ds resonant period as shown in figure 10.2. t res can be estimated to be approximately 2 s as a starting point and then adjusted after the power supply is tested. g a t e v d s t on t reset t res t period figure 10.2 : v ds timing when both criterion are met then (v in t on ) max can be determined by equation 10.8. ( ) 1 (max op) max (min) (max op) ( min) 11 1 where, in on sw indc tr out sw p qr vt f v nv f t ? ?? ?? ?? ?= + ?? ?? ?? ?? ?? = (10.8) where v indc(min) is the minimum input voltage across the bulk capacitor. in order to avoid input undervoltage detection during normal operation, v indc(min) should be set above the input undervoltage shutdown limit. (min) vin in indc uvdc in rz vv z + >? (10.9) assuming t res is 2 s then: ( ) min 10 p qr ts >m ' ( min) 1 2 11.1 110 p qr t ss khz > +m= m (min) 5.1 0.369 76 25 indc mk v vv k w + 25 w > = w to give some margin, we use 79 v for v indc(min) in equation 10.8, ( ) ( ) sw(max op) ( min) 1 11 79 6 12.5 max choosing, 72 and t 14 72 534 p qr in on vv khz s v t khz v s ? ?= =m ?? ? = + = ?m ?? also, to provide enough margin for component values, usually: ( ) ( ) max limit 0.85 in on in on vt vt ? IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 13 n ovembe r 27, 2012 since we calculated 534 vs as our v in t on we have enough margin. 10.6 magnetizing inductance a feature of the IW1710 is the lack of dependence on the magnetizing inductance for the cc curve. although the constant current limit does not depend on the magnetizing inductance, there are still restrictions on the magnetizing inductance. the maximum l m is limited by the amount of power that needs to come out of the transformer in order for the power supply to regulate. this is given by: ( ) 2 (max op) max (max) (max) (max) 2 in on sw m xfmr out out xfmr x vt f l p vi p ? = = h (10.11) where x is the effciency of the transformer, for this example we assume its 87 %. ( ) (max) 2 (max) 12.5 1.2 17.2 0.87 534 72 0.597 2 17.2 xfmr m va pw v s khz l mh w = = ?m = = the minimum l m is limited by the maximum allowable peak primary current. v reg-th corresponds to the maximum i sense voltage. see section 10.11 to calculate r isense . therefore l m is limited by: ( ) max (min) 2 (max op) 2 xfmr m reg th sw isense p l v f r ? = ?? ?? ?? (10.12) ( ) (min) 2 2 12.5 1.2 0.486 1.0 72 m va l mh v khz = = 1.08w for this example, we choose l m to be 0.577 mh. if these limits do not give enough tolerance for l m , increasing (v in t on ) max can raise the maximum limit on l m . take care not to go above (v in t on ) limit . also, keep in mind that if equation 10.6 and 10.7 are not met then (v in t on ) max does not occur at full load and lowest input voltage, thus some of the equations here would be invalid. 10.7 primary winding in order to keep the transformer from saturation, the maximum fux density must not be exceeded. therefore the minimum primary winding must meet: ( ) max max in on pri e vt n ba ? (10.13) where b max is maximum allowed fux density and a e is the core area. from the transformer core datasheet we fnd that for this example b max is 300 mt. for an ee19 core, a e is 22.6 mm 2 . 2 534 83.0 320 20.1 pri vs nt mt mm ?m = for this example, we choose 90 primary turns. 10.8 secondary winding from the primary winding turns, we obtain the secondary winding. pri sec tr n n n = (10.14) thus, in our example: 90 15 6 sec t nt = = 10.9 bias winding and v cc capacitance v cc is the supply to the IW1710 and should be below 16 v. the bias winding needs to ensure than v cc does not exceed 16 v during normal operation. ( ) sec cc fd bias out nvv n v + = (10.15) set v cc at around 10 v 15 10.5 12 12.5 bias tv nt v = = choose a value for n bias to be close to this number, for this example we choose 12 turns. the v cc capacitor (c vcc ) stores the v cc charge during ic operation and the controller checks this voltage and makes sure it is within range before starting and operating. the startup time is a function of how quickly this capacitor can charge up. () 2 cc inac vin v cc st start up v inst r cv t i ? = ? (10.16) 10.10 v sense resistors and winding the output voltage regulation is mainly determined by the feedback signal v sense . IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 14 n ovembe r 27, 2012 _ sense out pcb sense vv k = (10.17) where: ( ) bvsns vsense sense bvsns tvsns sec rn k rr n = + (10.18) internally, v sense is compared to a reference voltage v sense(nom) . where, v sense(nom) is 1.538 v. () _ sense nom sense out pcb v k v = (10.19) 1.538 0.128 12.0 sense v k v = = from here we can fnd the ratio necessary for r bvsns and r tvsns . for this example we set r tvsns to be 24 k. assuming we use the same winding for both v sense and v cc : 12 0.128 24 15 4.57 bvsns bvsns bvsns r t r kt rk = +w =w at this point the transformer design is complete. this would be a good time to confrm that this transformer is feasible to build. 10.11 current sense resistor the i sense resistor determines the maximum current output of the power supply. the output current of the power supply is determined by: 1 () 2 reset out tr pri pk x period t i ni t = h (10.20) when the maximum current output is achieved the voltage seen on the i sense pin (v isense ) should reach its maximum. thus, at constant current limit: () () isense cc pri pk isense v i r = (10.21) substituting this into equation 10.20 we get: () period isense cc c reset t vk t = (10.22) for IW1710 k c is 0.5 v, therefore r isense depends on the maximum output current by; 2 tr c isense x out nk r i = h (10.23) from table 10.1 i out is given to be 1.2 a, therefore r isense is: 6 0.5 0.87 1.08 2 1.2 isns v r a = =w we recommend using 1% tolerance resistors for r isense . 10.12 input bulk capacitor the input bulk capacitor, c bulk is chosen to maintain enough input power to sustain constant output power even as the input voltage is dropping. in order for this to be true c bulk must be: ( ) (min) (min) 1 2 2 22 (min) (min) () power supply 2 0.25 arcsin 2 indc inac v in v bulk inac indc line out cable out in p c vv f vi p ?? ?? + ?? ?? ?? ?? = ? = h (10.24) v inac(min) is the minimum input voltage (rms) to be inputted into the power supply and f line is the lowest line frequency for the power supply (in this case 47 hz). v indc(min) is calculated from equation 10.9. ( ) ( ) ( ) ( ) 79 1 2 2 85 2 2 12.5 1.2 20.8 0.72 2 20.8 0.25 arcsin 39 2 85 79 47 ac in v v bulk ac va pw w cf v v hz = = ?? + ?? ?? = = m ? 10.13 output capacitance the output capacitance affects both the steady state ripple and the dynamic response of the power supply. assuming an ideal capacitor where esr (equivalent series resistance) and esl (equivalent series inductance) are negligible then: (steady state) () out out out ripple q c v = (10.25) the output capacitor supplies the load current when the secondary current is below the output current. ( ) 2 () 2 2 m sec pk out out tr x out li i q nv ? = h (10.26) the i sec(pk) is: ( ) () in on max sec pk tr x m vt in l ? = h (10.27) so to keep v out(ripple) to be 100 mv, IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 15 n ovembe r 27, 2012 () 534 6 0.87 5.152 0.541 sec pk vs ia mh ?m = = ( ) 2 2 0.541 5.152 1.2 10.8 2 6 0.87 12.5 out mh a a qc v ? = = m (steady state) 10.8 208 100 out c cf mv m = = m in this calculation esr and esl are ignored; the reason this calculation is still valid is because of the second stage lc flter on the output of the supply. these two components reduce the esr and esl ripple; however keep in mind that the ripple is a little higher in reality than this calculation would suggest. assume that the load transient goes from no load to i out(high) . then from section 9.5, equation 9.8 we fnd that the relationship between output capacitance (c out(dynamic) ) and v drop(ic) is : ( ) ( ) (no load) dynamic () p out high out drop ic it c v = (10.28) then solving for v drop(ic) from figure 9.4, where v dynamic(drop) is the maximum allowable drop in voltage for the design during dynamic response, v drop(cable) is the drop in voltage due to the cable resistance, and v drop(sense) is the drop in voltage before v sense signal is low enough to register a dynamic transient. ( ) ( ) (no load) dynamic ()()() p out high out dynamic drop drop cable drop sense it c v vv = ?? (10.29) where t p(no load) is the maximum period under no load condition, given by equation 10.30: ( ) ( ) 2 preload no load no load 2 2 in on pfm p m out r vt t lv ? = h (10.30) assume that we want no more than 1.0 v drop on v out(pcb) during load transient from no load to 50% load and the effciency of the power supply at no load ( no load ) is 50% , then c out(dynamic) is: ( ) ( ) ( ) 2 2 5.6 119 461 2 0.541 12.5 p pfm k vs ts mh v w ?m = = m since there is no cable, v drop(cable) is 0 v. ( ) () 12.0 1.538 1.48 0.543 1.538 drop sense v v vv v v = ? = plug everything into equation 10.19: ( ) dynamic 0.5 461 504 1.0 0 0.543 out as cf vv v m = = m ?? pick the larger capacitance value between c out(dynamic) and c out(steady state) . in this case c out is chosen to be 680 f. 10.14 snubber network the snubber network is implemented to reduce the voltage stress on the mosfet immediately following the turn off of the gate drive. the goal is to dissipate the energy from the leakage inductance of the transformer. for simplicity and a more conservative design frst assume the energy of the leakage inductance is only dissipated through the snubber. thus: 2 22 11 () () ( ) 22 lk pri pk snub snub pk snub val li c v v ?? = ? ?? (10.31) l lk can be measured from the transformer and v ds is the voltage across the mosfet. v snub(pk) and v snub(val) refer to the voltage measured across the snubber capacitor. choose a c snub , keeping in mind that the larger the value of c snub the lower the voltage stress is on the mosfet. however, capacitors are more expensive the larger their capacitance. choose c snub based on these two criteria and select v snub(pk) and v snub(val) . now a resistor needs to be selected to dissipate v snub(pk) to v snub(val) during the on-time of the gate driver. the dissipation of this resistor is given by: ( min op) () () t p rc snub snub snub val snub pk v e v ? ? = (10.32) using equation 10.32 solve for r snub . this gives a conservative estimate of what c snub and r snub should be. included in the snubber network is also a resistor in series with a diode. the diode directs current to the snubber capacitor when the mosfet is turned off; however there is some reverse current that goes through the diode immediately after the mosfet is turned back on. this reverse current occurs because there is a short period of time when the diode still conducts after switching from forward biased to reverse biased. this conduction distorts the falling edge of the v sense signal and affects the operation of the ic. so, the resistor in series with the diode is there to diminish the reverse current that goes through the diode immediately after the mosfet is turned on. 10.15 t on delay filter IW1710 also contains a feature that allows for adjustment to match high line and low line constant current curves. the mismatch in high line and low line is due to the delay from the ic propagation delay, driver turn-on delay, and the mosfet turn-on delay. the driver turn-on delay maybe IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 16 n ovembe r 27, 2012 further increased by a gate resistor to the mosfet. to adjust for these delays the IW1710 factors these delays into its calculations and slightly over compensates for them to provide fexibility. r dly and c dly provide extra delay in the circuit to tweak the compensation. to determine values r dly and c dly follow these steps: 1. measure the difference between high line and low line constant current limit without flter components. 2. find the curve that best matches this difference from figure 11.1. 3. find the l m that matches the power supply, and fnd the t rc . 4. find r dly and c dly from equation 10.33 rc dly dly rc t= (10.33) 10.16 sd protection the sd pin can be confgured to provide three different types of protection: otp protection, ovp protection and both ovp and otp protection. figure 10.3 shows the three confgurations plus the confguration for no otp and ovp protection. sd pin output sd pin sd pin sd pin a) overtemperature protection only b) overtemperature protection and overvoltage protection c) overvoltage protection only d) no overtemperature protection and no overvoltage protection r ntc r sd(ext) (optional) r ntc r sd1(ext) r sd(ext) r sd(ext) r sd2(ext) figure 10.3 : 63lssolfdwlrrudwlrv otp only to detect an overtemperature protection the IW1710 sends a 107 m a current (i sd ) to the sd pin every four cycles (see section 9.13). on the last cycle the IW1710 observes the voltage on the sd pin and detects an otp fault if the voltage is lower than v sd-th , 1.0 v during normal operation and 1.2 v during startup. so r sd(ext) in series with ntc must meet ( ) () ntc sd ext sd sd th r r iv ? + > (10.34) in order not to trigger otp fault during normal operation. ovp only for the other four cycles, the IW1710 connects the sd pin to r sd to ground (see section 9.13). at the last cycle the IW1710 observes the voltage on the sd pin and detects an ovp fault if the voltage is higher than v sd-th , 1 v. in order to not trigger ovp fault, assuming 0 v drop across the series diode, r sd(ext) must meet: _ () out pcb sd aux sd th sec sd sd ext v r nv n rr ? < + (10.35) where, r sd = 8.333 k both otp and ovp to fnd r sd1(ext) so that ovp can be detected, use equation 10.35. to fnd r sd2(ext) in series with the ntc use equation 10.34. no otp and ovp if otp and ovp from the sd pin are not needed, simply place a resistor, r sd(ext) to ground from the sd pin. make sure r sd(ext) meets equation 10.36 so otp protection does not trip. () sd ext sd sd th r iv ? > (10.36) note that this means ovp is not detected through the sd pin; however, ovp from v sense pin is still active and the IW1710still shuts down if overvoltage condition is detected. since for this example otp and ovp are not necessary we place a resistor from sd pin to ground and calculate its value from equation 10.36. () 1.2 12 100 sd ext v rk a >=w m 10.17 pcb layout in the IW1710, there are two signals that are important to control the output performance; these are the i sense signal and the v sense signal. the i sense resistor should be close to the source of the mosfet to avoid any trace resistance from contaminating the i sense signal. also, the i sense signal should be placed close to the i sense pin. the v sense signal should be placed close to the transformer to improve the quality of the sensing signal. also for better output performance all IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 17 n ovembe r 27, 2012 bypass capacitors should be placed close to their respective pins. to reduce emi, switching loops need to be minimized. these loops include: 1. the input bulk capacitor, primary winding, mosfet and r isense loop. 2. the output diode, output capacitor and secondary winding loop. 3. v cc winding and rectifer diode loop. l n v out rtn + + + u1 IW1710 optional ntc thermistor nc v sense v in sd v cc output i sense gnd 1 2 3 8 7 6 4 5 1) 2) 3) figure 10.4 : switching loops to improve esd performance provide a low impedance path from the ground pin of the transformer to the ac power source and make sure this path does not go through the ic ground pin. a discharge spark gap helps to transfer esd and eos energy from the secondary side of the power supply directly to the external ac power source. in a switch-mode power supply there are several ground signals, namely: the power ground, the switching ground and the control logic ground. these ground signals should be connected by a star connection. ground traces should be kept as short as possible. a thick trace on the switching ground helps to lessen switching losses. IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 18 n ovembe r 27, 2012 11.0 design example performance characteristics 12.0 application circuit figure 11.1 : t on compensation chart figure 12.1 : typical application circuit l n v out rtn + + + u1 IW1710 + csnub rsnub rvin rvin cdly (opt) rdly (opt) risense cvcc nc v sense v in sd v cc output i sense gnd 1 2 3 8 7 6 4 5 rtvsns rbvsns cbulk cbulk cout rntc rpreload 4.57 k? 24.0 k? 2.7 m? 2.4 m? 4.7 f 1000 ? 33 pf 1.08 ? 20 k? 10 f 33 f 1 nf 680 f 5.6 k? 68 ? 75 k? 22 ? 4.7 ? 10 k? 470 h 1 a / 250 v 470 pf 22 pf rgate (opt): optional ( r dly x c dly ), rc (ns) magnetizing inductance l m (mh) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 50 ma 40 ma 30 ma 20 ma 10 ma ?i out (note1) note 1: , out uhhuvwrwhlhuhqfhlqfrqvwqwfuuhqwolplwhwzhhq9 ac and 90 v ac when no r < and c < uholh IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 19 n ovembe r 27, 2012 13.0 physical dimensions figure 13.1 : physical dimensions, 8-lead soic package compliant to jedec standard ms12f controlling dimensions are in inches; millimeter dimensions are for reference only this product is rohs compliant and halide free. soldering temperature resistance: [a] package is ipc/jedec std 020d moisture sensitivity level 1 [b] package exceeds jedec std no. 22-a111 for solder immersion resistance; package can withstand 10 s immersion < 270?c dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extremes of the plastic bocy exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 8-lead small outline (soic) package coplanarity 0.10 (0.004) 8 5 4 1 seating plane a1 e h b d e a a2 c l h x 45 inches symbol millimeters min 0.0040 a1 max min max 0.010 0.10 0.25 0.053 a 0.069 1.35 1.75 0.014 b 0.019 0.35 0.49 0.007 c 0.010 0.19 0.25 0.189 d 0.197 4.80 5.00 0.150 e 0.157 3.80 4.00 0.050 bsc e 1.27 bsc 0.228 h 0.244 5.80 6.20 0.10 h 0.020 0.25 0.50 0.016 l 0.049 0.4 1.25 0 8 0.049 a2 0.059 1.25 1.50 14.0 ordering information part number options package description IW1710-01 cable comp = 0 mv soic-8 tape & reel 1 IW1710-21 cable comp = 300 mv soic-8 tape & reel 1 note 1: tape & reel packing quantity is 2,500/reel. IW1710 digital pwm current-mode controller for quasi-resonant operation
r ev . 2.5 i w1710 p age 20 n ovembe r 27, 2012 trademark information ? 2012 iwatt inc. all rights reserved. iwatt, broadled, ez-emi , flickerless, intelligent ac-dc and led power, and primaccurate are trademarks of iwatt inc. all other trademarks and registered trademarks are the property of their respective owners. contact information web: https://www.iwatt.com e-mail: info@iwatt.com phone : +1 (408) 374-4200 fax: +1 (408) 341-0455 iwatt inc. 675 campbell technology parkway, suite 150 campbell, ca 95008 disclaimer and legal notices iwatt reserves the right to make changes to its products and to discontinue products without notice. the applications information, schematic diagrams, and other reference information included herein is provided as a design aid only and are therefore provided as-is. iwatt makes no warranties with respect to this information and disclaims any implied warranties of merchantability or non-infringement of third-party intellectual property rights. this product is covered by the following patents: 6,385,059; 6,730,039; 6,862,198; 6,900,995; 6,956,750; 6,990,900; 7,443,700; 7,505,287; 7,589,983; 6,972,969; 7,724,547; 7,876,582; 7,880,447; 7,974,109; 8,018,743; 8,049,481. a full list of iwatt patents can be found at www. iwatt.com. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (critical applications). iwatt semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life - support applications, devices or systems, or other critical applications. inclusion of iwatt products in critical applications is understood to be fully at the risk of the customer. questions concerning potential risk applications should be directed to iwatt inc. iwatt semiconductors are typically used in power supplies in which high voltages are present during operation. high-voltage safety precautions should be observed in design and operation to minimize the chance of injury . IW1710 digital pwm current-mode controller for quasi-resonant operation

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